Using QSPI with Tricore SW Framework

Hello,
I've been trying to run the QSPI on the AURduino TC275 Shield for about 20 hours now - without success.
I'm using the Infineon Software Framework  for Tricore/Aurix TC275.
My IDE is TASKING C/C++ Tricore Eclipse IDE v6.0r1, my debugger pls UDE Desktop 4.04.07.

I use a direct usb connection for both debugging and UART. I successfully set up the Asclin UART Module and use this for outputting the SPI data to HTerm on my computer.
After initialization, the SCLK line successfully turns low (idle low). Then, in my main routine:



#define SPI_MEAS_CUR_BUFFER_SIZE 4
uint8 spi_meas_cur_tx_buffer[SPI_MEAS_CUR_BUFFER_SIZE] = { 0x55, 0x55, 0x55, 0x55 };
uint8 spi_meas_cur_rx_buffer[SPI_MEAS_CUR_BUFFER_SIZE] = { 0x00, 0x00, 0x00, 0x00 };

while (TRUE)
   {
    int i=0;
    // wait until transfer of previous data stream is finished
    while( IfxQspi_SpiMaster_getStatus(&spi_channel_cur) == SpiIf_Status_busy ); // after second run it hangs up here

    // send/receive new stream
    IfxQspi_SpiMaster_exchange(&spi_channel_cur, &spi_meas_cur_tx_buffer[i], &spi_meas_cur_rx_buffer[i], SPI_MEAS_CUR_BUFFER_SIZE);

    delay_ms(1000);
    uart_send_bit16(spi_meas_cur_rx_buffer[0], "TLI4970");
    delay_ms(100);
   }

Code compiles and runs on the CPU. Then, I can call "IfxQspi_SpiMaster_exchange(...)" once, then the SpiMaster stays busy. With the scope, I cannot trigger any activity on any of the lines (SCLK, Chipselect, MTSR). With the debugger i see that the BACON register didn't change at all. (I guess I can't read the DATAENTRY because its read only? It returns 0x00 anyway).

I tried it with/without DMA, on QSPI1, QSPI2, QSPI3 and with different chip selects (QSPI0 has no CS pinned out). Same behaviour in all modes.
How can I make my SPI work? Did I forget to activate something? (I'm calling __enable() in the init_isr())
See my full code below. Thank you very much for your support!
Best Regards,
Matthias


Cpu0_Main.c

/******************************************************************************/
/*----------------------------------Includes----------------------------------*/
/******************************************************************************/
#include <stdio.h>
#include <Cpu/Std/Ifx_Types.h>
#include <Stm/Std/IfxStm.h>
#include <Cpu/Irq/IfxCpu_Irq.h>
#include "Configuration.h"
#include <globals.h>
#include <uart.h>
#include <spi.h>
#include "Cpu_Main.h"
#include "Cpu0_Main.h"
#include "main_appl.h"

/******************************************************************************/
/*------------------------------Global variables------------------------------*/
/******************************************************************************/
App_Cpu g_AppCpu0; /**< \brief CPU 0 global data */
/* this variables are initialized by c_init and accessible from all CPUs */


/******************************************************************************/
/*-------------------------Function Implementations---------------------------*/
/******************************************************************************/


/** \brief Main entry point after CPU boot-up.
*
*  It initialises the system and enter the endless loop that handles the demo
*/
int core0_main(void)
{
   init();
   delay_ms(100);
   /* background endless loop */
   while (TRUE)
   {
    int i=0;
    // wait until transfer of previous data stream is finished
    while( IfxQspi_SpiMaster_getStatus(&spi_channel_cur) == SpiIf_Status_busy );

    // send/receive new stream
    IfxQspi_SpiMaster_exchange(&spi_channel_cur, &spi_meas_cur_tx_buffer[i], &spi_meas_cur_rx_buffer[i], SPI_MEAS_CUR_BUFFER_SIZE);

    delay_ms(1000);
    uart_send_bit16(spi_meas_cur_rx_buffer[0], "TLI4970");
    delay_ms(100);
   }

   //return 0;
}

void init()
{
disable_watchdogs();
init_clock();
init_uart();
init_spi();
init_isr();
}

void disable_watchdogs()
{
   /*
    * !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!!
    * Enable the watchdog in the demo if it is required and also service the watchdog periodically
    * */
   IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword());
   IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword());
}
void init_clock()
{
   /* Initialise the application state */
   g_AppCpu0.info.pllFreq = IfxScuCcu_getPllFrequency();
   g_AppCpu0.info.cpuFreq = IfxScuCcu_getCpuFrequency(IfxCpu_getCoreId());
   g_AppCpu0.info.sysFreq = IfxScuCcu_getSpbFrequency();
   g_AppCpu0.info.stmFreq = IfxStm_getFrequency(&MODULE_STM0);
   g_AppCpu0.TickCount_1ms = 0;

   IfxGtm_enable(&MODULE_GTM);
   // we set the global clock to 100MHz
   IfxGtm_Cmu_setGclkFrequency(&MODULE_GTM, 100000000.0f);
   // set CMU0 frequency
   IfxGtm_Cmu_setClkFrequency(&MODULE_GTM, IfxGtm_Cmu_Clk_0, 100000000.0f);
   // enable CMU0 clock
   IfxGtm_Cmu_enableClocks(&MODULE_GTM, IFXGTM_CMU_CLKEN_CLK0);
   // enable FX clock
   IfxGtm_Cmu_enableClocks(&MODULE_GTM, IFXGTM_CMU_CLKEN_FXCLK);
}

void init_isr()
{
/* globally enable Interrupts */
IfxCpu_enableInterrupts();
}


Cpu0_Main.h

#ifndef CPU0_MAIN_H_
#define CPU0_MAIN_H_

#define delay_ms( _milliseconds ) \
{for (unsigned int ii=0; ii < (_milliseconds * (IFX_CFG_SCU_XTAL_FREQUENCY/2000)); ii++) { __nop(); __nop(); }}
/* The two __nop() ("No operations") are necessary to halt the program during the execution of the delay functions. Some
debugger has problems with too short loops. */

void init(void);
void disable_watchdogs(void);
void init_clock(void);
void init_isr(void);
#endif /* CPU0_MAIN_H_ */

spi.c

#include <spi.h>

uint8 spi_meas_cur_tx_buffer[SPI_MEAS_CUR_BUFFER_SIZE] = { 0x55, 0x55, 0x55, 0x55 };
uint8 spi_meas_cur_rx_buffer[SPI_MEAS_CUR_BUFFER_SIZE] = { 0x00, 0x00, 0x00, 0x00 };

IfxQspi_SpiMaster spi;
IfxQspi_SpiMaster_Channel spi_channel_cur;
IfxQspi_SpiMaster_Config spi_master_config;

void init_spi()
{
#ifdef QSPI2_USE_DMA
IfxSrc_init(&MODULE_SRC.DMA.DMA[0].CH[SPI_MEAS_DMA_CH_TXBUFF_TO_TXFIFO], IfxSrc_Tos_dma, SPI_MEAS_DMA_CH_TXBUFF_TO_TXFIFO);
IfxSrc_init(&MODULE_SRC.DMA.DMA[0].CH[SPI_MEAS_DMA_CH_RXBUFF_FROM_RXFIFO], IfxSrc_Tos_dma, SPI_MEAS_DMA_CH_RXBUFF_FROM_RXFIFO);
IfxSrc_enable(&MODULE_SRC.DMA.DMA[0].CH[SPI_MEAS_DMA_CH_TXBUFF_TO_TXFIFO]);
IfxSrc_enable(&MODULE_SRC.DMA.DMA[0].CH[SPI_MEAS_DMA_CH_RXBUFF_FROM_RXFIFO]);
#else
IfxSrc_init(&MODULE_SRC.QSPI.QSPI[SPI_MEAS_NUMBER].TX, IfxCpu_Irq_getTos(IfxCpu_getCoreIndex()), IFX_PRIORITY_SPI_MEAS_TX);
IfxSrc_init(&MODULE_SRC.QSPI.QSPI[SPI_MEAS_NUMBER].RX, IfxCpu_Irq_getTos(IfxCpu_getCoreIndex()), IFX_PRIORITY_SPI_MEAS_RX);
IfxSrc_enable(&MODULE_SRC.QSPI.QSPI[SPI_MEAS_NUMBER].TX);
IfxSrc_enable(&MODULE_SRC.QSPI.QSPI[SPI_MEAS_NUMBER].RX);
#endif
IfxSrc_init(&MODULE_SRC.QSPI.QSPI[SPI_MEAS_NUMBER].ERR, IfxCpu_Irq_getTos(IfxCpu_getCoreIndex()), IFX_PRIORITY_SPI_MEAS_ER);
IfxSrc_enable(&MODULE_SRC.QSPI.QSPI[SPI_MEAS_NUMBER].ERR);

// create module config
IfxQspi_SpiMaster_initModuleConfig(&spi_master_config, &SPI_MEAS_MODULE);

// set the desired mode and maximum baudrate
spi_master_config.base.mode             = SpiIf_Mode_master;
spi_master_config.base.maximumBaudrate  = 10000000;

// ISR priorities and interrupt target
spi_master_config.base.txPriority       = IFX_PRIORITY_SPI_MEAS_TX;
spi_master_config.base.rxPriority       = IFX_PRIORITY_SPI_MEAS_RX;
spi_master_config.base.erPriority       = IFX_PRIORITY_SPI_MEAS_ER;
#ifdef QSPI2_USE_DMA
spi_master_config.dma.txDmaChannelId = SPI_MEAS_DMA_CH_TXBUFF_TO_TXFIFO;
spi_master_config.dma.rxDmaChannelId = SPI_MEAS_DMA_CH_RXBUFF_FROM_RXFIFO;
spi_master_config.dma.useDma = TRUE;
#else
spi_master_config.base.isrProvider      = IfxCpu_Irq_getTos(IfxCpu_getCoreIndex());
#endif

// pin configuration
const IfxQspi_SpiMaster_Pins pins = {
   &SPI_MEAS_SCLK_PIN, IfxPort_OutputMode_pushPull, // SCLK
   &SPI_MEAS_MTSR_PIN, IfxPort_OutputMode_pushPull, // MTSR
   &SPI_MEAS_MRST_PIN, IfxPort_InputMode_pullDown,  // MRST
   IfxPort_PadDriver_cmosAutomotiveSpeed3 // pad driver mode
};
spi_master_config.pins = &pins;

// initialize module
//IfxQspi_SpiMaster spi; // defined globally
IfxQspi_SpiMaster_initModule(&spi, &spi_master_config);

init_spi_channel_cur();
}

void init_spi_channel_cur()
{
// create channel config
IfxQspi_SpiMaster_ChannelConfig spi_master_channel_config;
IfxQspi_SpiMaster_initChannelConfig(&spi_master_channel_config, &spi);

// set the baudrate for this channel
spi_master_channel_config.base.baudrate = 1000000;

// select pin configuration
IfxQspi_SpiMaster_Output sls_output = {
&SPI_MEAS_CS_CUR_PIN,
IfxPort_OutputMode_pushPull,
IfxPort_PadDriver_cmosAutomotiveSpeed1
};
spi_master_channel_config.sls.output = sls_output;

// initialize channel
//IfxQspi_SpiMaster_Channel spi_channel; // defined globally
IfxQspi_SpiMaster_initChannel(&spi_channel_cur, &spi_master_channel_config);
}

#ifdef QSPI2_USE_DMA
IFX_INTERRUPT(qspiMeasDmaTxISR, 0, IFX_PRIORITY_SPI_MEAS_TX )
{
   IfxQspi_SpiMaster_isrDmaTransmit(&spi);
}

IFX_INTERRUPT(qspiMeasDmaRxISR, 0, IFX_PRIORITY_SPI_MEAS_RX)
{
  IfxQspi_SpiMaster_isrDmaReceive(&spi);
}
#else
IFX_INTERRUPT(qspiMeasTxISR, 0, IFX_PRIORITY_SPI_MEAS_TX)
{
   IfxQspi_SpiMaster_isrTransmit(&spi);
}

IFX_INTERRUPT(qspiMeasRxISR, 0, IFX_PRIORITY_SPI_MEAS_RX)
{
   IfxQspi_SpiMaster_isrReceive(&spi);
}

#endif

IFX_INTERRUPT(qspiMeasErISR, 0, IFX_PRIORITY_SPI_MEAS_ER)
{
   IfxQspi_SpiMaster_isrError(&spi);
}



spi.h

#ifndef SPI_H_
#define SPI_H_

#include <Qspi/SpiMaster/IfxQspi_SpiMaster.h>
#include <Cpu/Irq/IfxCpu_Irq.h>
#include <Configuration.h>
#include <globals.h>

void init_spi(void);
void init_spi_channel_cur(void);

#ifdef QSPI2_USE_DMA
IFX_INTERRUPT(qspiMeasDmaTxISR, 0, IFX_PRIORITY_SPI_MEAS_TX );
IFX_INTERRUPT(qspiMeasDmaRxISR, 0, IFX_PRIORITY_SPI_MEAS_RX);
#else
IFX_INTERRUPT(qspiMeasTxISR, 0, IFX_PRIORITY_SPI_MEAS_TX);
IFX_INTERRUPT(qspiMeasRxISR, 0, IFX_PRIORITY_SPI_MEAS_RX);
#endif
IFX_INTERRUPT(qspiMeasErISR, 0, IFX_PRIORITY_SPI_MEAS_ER);

#endif /* SPI_H_ */



globals.h

#ifndef GLOBALS_H_
#define GLOBALS_H_
#include <Asclin/Asc/IfxAsclin_Asc.h>
#include <Configuration.h>

/********************************************************
*  uart.c
********************************************************/
/* UART Interface */
extern IfxAsclin_Asc uart;
extern uint8 uart_tx_buf[ASC_TX_BUFFER_SIZE + sizeof(Ifx_Fifo) + 8];
extern uint8 uart_rx_buf[ASC_RX_BUFFER_SIZE + sizeof(Ifx_Fifo) + 8];

/********************************************************
*  spi.c
********************************************************/
extern uint8 spi_meas_cur_tx_buffer[SPI_MEAS_CUR_BUFFER_SIZE];
extern uint8 spi_meas_cur_rx_buffer[SPI_MEAS_CUR_BUFFER_SIZE];
extern IfxQspi_SpiMaster spi;
extern IfxQspi_SpiMaster_Channel spi_channel_cur;

#endif /* 0_SRC_0_APPSW_TRICORE_GLOBALS_H_ */



Configuration.h
#ifndef CONFIGURATION_H
#define CONFIGURATION_H
/******************************************************************************/
/*----------------------------------Includes----------------------------------*/
/******************************************************************************/
#include "Ifx_Cfg.h"
#include <_PinMap/IfxQspi_PinMap.h>
#include <_PinMap/IfxPort_PinMap.h>
#include <_PinMap/IfxScu_PinMap.h>
#include <_PinMap/IfxGtm_PinMap.h>
#include <_PinMap/IfxAsclin_PinMap.h>
#include <Tricore/Qspi/Qspi0.h>
#include <Tricore/Qspi/Qspi1.h>
#include <Tricore/Qspi/Qspi2.h>
#include <Tricore/Qspi/Qspi3.h>
#include "ConfigurationIsr.h"

/******************************************************************************/
/*-----------------------------------Macros-----------------------------------*/
/******************************************************************************/

/* set here the used pins for QSPI1 */
#define QSPI1_MAX_BAUDRATE           50000000  // maximum baudrate which is possible to get a small timequantum
#define QSPI1_SCLK_PIN           IfxQspi1_SCLK_P10_2_OUT
#define QSPI1_MTSR_PIN           IfxQspi1_MTSR_P10_3_OUT
#define QSPI1_MRST_PIN             IfxQspi1_MRSTA_P10_1_IN
//#define QSPI1_USE_DMA   // uncomment line for using DMA
//#define DMA_CH_QSPI1_TX             SPI_MEAS_DMA_CH_TXBUFF_TO_TXFIFO
//#define DMA_CH_QSPI1_RX             SPI_MEAS_DMA_CH_RXBUFF_FROM_RXFIFO
#define SPI_MEAS_INIT qspi1_init
#define SPI_MEAS_NUMBER 1
#define SPI_MEAS_MODULE MODULE_QSPI1
#define SPI_MEAS_SCLK_PIN QSPI1_SCLK_PIN
#define SPI_MEAS_MTSR_PIN QSPI1_MTSR_PIN
#define SPI_MEAS_MRST_PIN QSPI1_MRST_PIN
#define SPI_MEAS_CS_CUR_PIN IfxQspi1_SLSO9_P10_5_OUT

#define SPI_MEAS_CUR_BAUD 1000000
#define SPI_MEAS_CUR_DATAWIDTH 16 /* TLI: 16bit, MCP3208: 24bit oder sogar 19 */
#define SPI_MEAS_CUR_CSLEADDELAY SpiIf_SlsoTiming_1 /* 1 half-clock delay (500ns @ 1MHz, MCP3208: 100ns, TLI4970: 95ns) */
#define SPI_MEAS_CUR_CSTRAILDELAY SpiIf_SlsoTiming_1 /* 1 half-clock delay (500ns @ 1MHz, MCP3208: n.A., TLI4970: 95ns) */
#define SPI_MEAS_CUR_CSINACTDELAY SpiIf_SlsoTiming_2 /* 3 half-clock delay (1500ns @ 1MHz, MCP3208: 500ns, TLI4970: 300ns) */
#define SPI_MEAS_CUR_SHIFTTX SpiIf_ShiftClock_shiftTransmitDataOnLeadingEdge
#define SPI_MEAS_CUR_DATAHEAD SpiIf_DataHeading_msbFirst
#define SPI_MEAS_CUR_CLKPOL SpiIf_ClockPolarity_idleLow

#define SPI_MEAS_CUR_BUFFER_SIZE 4 // 16


/* UART Module */
#define UART_BAUDRATE 115200 /* max. empfohlene Übertragungslänge 2m */
#define UART_BAUDRATE_PRE 1
#define UART_TX_BUF_NUM_CMDS 16
#define UART_TX_BUF_NUM_CMD_WORDS 42 /* 40 Byte + \n + \0 */
#define UART_RX_BUF_NUM_CMDS 8
#define UART_RX_BUF_NUM_CMD_WORDS 22 /* 20 Byte + \n + \0 */
#define ASC_TX_BUFFER_SIZE (UART_TX_BUF_NUM_CMDS * UART_TX_BUF_NUM_CMD_WORDS)
#define ASC_RX_BUFFER_SIZE (UART_RX_BUF_NUM_CMDS * UART_RX_BUF_NUM_CMD_WORDS)
#define UART_TX_TIMEOUT_TICKS 1000
#define ASC_TXD_USE                 IfxAsclin3_TX_P15_7_OUT /* IfxAsclin0_TX_P15_2_OUT */
#define ASC_RXD_USE                 IfxAsclin3_RXD_P32_2_IN/* IfxAsclin0_RXB_P15_3_IN */
#define UART_TX_IRQ MODULE_SRC.ASCLIN.ASCLIN[3].TX // I use HW Interrupts. This works perfectly for Asclin UART-Module
#define UART_RX_IRQ MODULE_SRC.ASCLIN.ASCLIN[3].RX
#define UART_ERR_IRQ MODULE_SRC.ASCLIN.ASCLIN[3].ERR
#define UART_TXDATA ASCLIN3_TXDATA
#define UART_RXDATA ASCLIN3_RXDATA
#define UART_MODULE MODULE_ASCLIN3

/* set the values for systemtimer */
#define IFX_CFG_STM_TICKS_PER_MS (100000) /**< \brief Number of STM ticks per millisecond */

#endif


ConfigurationIsr.h


#ifndef CONFIGURATIONISR_H
#define CONFIGURATIONISR_H

#include <_Impl/IfxSrc_cfg.h>
#define IFX_INTPRIO_UART_RX 15
#define IFX_PRIORITY_SPI_MEAS_RX 20  /**< \brief Define the Measurement Qspi receive interrupt priority.  */
#define IFX_PRIORITY_SPI_MEAS_TX 21  /**< \brief Define the Measurement Qspi transmit interrupt priority.  */
#define IFX_INTPRIO_UART_TX 25
#define IFX_INTPRIO_UART_ER 35
#define IFX_PRIORITY_SPI_MEAS_ER 40  /**< \brief Define the Measurement Qspi error interrupt priority.  */

#define ISR_PRIORITY_QSPI1_TX IFX_PRIORITY_SPI_MEAS_TX
#define ISR_PRIORITY_QSPI1_RX IFX_PRIORITY_SPI_MEAS_RX
#define ISR_PRIORITY_QSPI1_ER IFX_PRIORITY_SPI_MEAS_ER

/** \} */

/**
* \name DMA channel configuration.
* The DMA channel range is [0,15] for TC22X/TC23X
* \{
*/

#define SPI_MEAS_DMA_CH_TXBUFF_TO_TXFIFO   IfxDma_ChannelId_0 /**< \brief Dma channel used for Qspi Transmit for Measurement with MCP3208/TLI4970  */
#define SPI_MEAS_DMA_CH_RXBUFF_FROM_RXFIFO IfxDma_ChannelId_1 /**< \brief Dma channel used for Qspi Receive for Measurement with MCP3208/TLI4970  */
// DMA is disabled in this example

/** \} */

/**
* \name Interrupt service provider configuration (use only number for variable section definition).
* \{ */
#define ISR_PROVIDER_QSPI1          IfxSrc_Tos_cpu0     /**< \brief Define the Qspi1 interrupt provider.  */

/** \} */

//------------------------------------------------------------------------------

#endif