Problem-UART(ASC3) not working with DMA

Hi,
I am trying to send 8-bit data from an array (stored in RAM) over UART TX line using DMA. I have configured ASC3 as UART and also configured DMA channel 14 to do so. I have put the configurations as below. When I run the program with this configuration, I only get 1st byte of the array. Kindly help me and let me know which configuration I am missing or doing it wrong. I am using shield buddy board and HIGHTEC toolchain compiler. The UART TX and RX with interrupt installed on CPU0 works without any problem. But, facing problem when I route UART TX to DMA channel.

void ASC3_vInit(void)

{

// USER CODE BEGIN (Init,2)

volatile unsigned int dummy;

// USER CODE END



uartRxBufferIdx = 0;

uartRxEOLDetected = GTF_FALSE;



MAIN_vResetENDINIT();



ASCLIN3_CLC.B.DISR = 0; // enable module

dummy = ASCLIN3_CLC.U; // dummy read to flush pipeline

dummy = dummy;

MAIN_vSetENDINIT();



ASCLIN3_CSR.U = 0; // clock off



//ASCLIN3_IOCR.B.LB = 1; // loopback mode on



// ASCLIN3_TXFIFOCON.B.INW = 1; // 1 byte input width

ASCLIN3_TXFIFOCON.B.INW = 1; // 1 byte input width

ASCLIN3_TXFIFOCON.B.ENO = 1; //enable TX FIFO

ASCLIN3_TXFIFOCON.B.INTLEVEL = 0;

ASCLIN3_TXFIFOCON.B.FLUSH = 1;



ASCLIN3_RXFIFOCON.B.OUTW = 1; // 1 byte output width

ASCLIN3_RXFIFOCON.B.ENI = 1; //enable RX FIFO

ASCLIN3_RXFIFOCON.B.INTLEVEL = ASC3_UART_RXFIFO_LEVEL - 1;

ASCLIN3_RXFIFOCON.B.FLUSH = 1;



ASCLIN3_FRAMECON.B.STOP = 1;



ASCLIN3_DATCON.B.DATLEN = 7; //8bit



ASCLIN3_BITCON.U = 0x890F0000; // OS 16, SP 7,8,9, PS 1

ASCLIN3_BRG.B.NUMERATOR = (16*1); // set for 1 * 100.000 bps

ASCLIN3_BRG.B.DENOMINATOR = 1000;



//ASCLIN3_BITCON.U = 0x890F0009; // OS 16, SP 7,8,9, PS 10

//ASCLIN3_BRG.B.NUMERATOR = 0x240; //115200

//ASCLIN3_BRG.B.DENOMINATOR = 0xC35; //3125 dec.



ASCLIN3_FLAGSCLEAR.U = 0xFFFFFFFF; // clear all flags

//ASCLIN3_FLAGSENABLE.U = 0x30000000; // Enable only RX Int.

ASCLIN3_FLAGSENABLE.U = 0xF0000000; // Enable TX & RX Int.

SRC_ASCLIN3RX.U = 0x0000040F; //Enable 'SRE' & assign 'SRPN' to 15 and map RX INT to CPU0



// This line activated the SW ISR:

//SRC_ASCLIN3TX.U = (0x0000040E); //Enable 'SRE' & assign 'SRPN' to ASC3TX_PRIO and map TX INT to CPU0



// These two activate the DMA

SRC_ASCLIN3TX.U = (0x0000180E); // assign 'SRPN' to 14 and map TX INT to DMA

SRC_ASCLIN3TX.U |= 0x00000400; //Enable 'SRE'



//install handler for ASC3 UART RX interrupt

_install_int_handler((unsigned char)ASC3RX_PRIO, (void (*) (int)) UART_ASC3_RX_ISR, 0);

//_install_int_handler((unsigned char)ASC3TX_PRIO, (void (*) (int)) UART_ASC3_TX_ISR, 0);



// P15.7 as TX output pin as per www.hitex.co.uk/fileadmin/uk-files/pdf/AurduinoUserManual.pdf

P15_IOCR4.B.PC7 = 0x12; //alternate function: ATX3



P20_IOCR0.B.PC0 = 0x12; //alternate function: ATX3



ASCLIN3_IOCR.U = 0; // disable CTS handling no glitch filter, no loopback

// P32.2 as input as per Table 18-5 ASCLIN I/O Control Selection and Setup in TC27xC UM

P32_IOCR0.B.PC2 = 0; // P32.2 as input

ASCLIN3_IOCR.B.ALTI = 3; // ARX3D /P32.2

//ASCLIN3_IOCR.B.ALTI = 2; // ARX3C /P20.3



ASCLIN3_FRAMECON.B.MODE = 1; // ASC mode



ASCLIN3_CSR.B.CLKSEL = 1; // turn on ASC clock, TC27xC UM says fCLC but probably means fSPB



} // End of function ASC3_vInit


void DMA_vInit(void)

{

unsigned int i = 0;

volatile unsigned long dummy = 0;

/* while(i<255)

{

uartTxBuffer = (char)(i+'a');

i++;

}



while(i<255)

{

uartTxBuffer = (char)(i+'a');

i++;

}







MAIN_vResetENDINIT();

DMA_CLC.U = 0x08; // enable module

dummy = DMA_CLC.U; // dummy read to flush pipeline

dummy = dummy;

MAIN_vSetENDINIT();



/* restart DMA controller */

DMA_TSR014.B.DCH = 1; /* disable HW request */

DMA_TSR014.B.RST = 1; /* reset transfer request */

while(DMA_TSR014.B.RST != 0); /* wait until reset is done */


//DMA_SADR014.U = (unsigned long)&uartTxBuffer[0]; //set DMA channel src address

DMA_SADR014.U = (unsigned long)&uartTxBuffer[16]; //set DMA channel src address

DMA_DADR014.U = (unsigned long)&ASCLIN3_TXDATA.U; //set DMA channel destination address

DMA_ADICR014.B.INCS = 1; //auto increment source address

DMA_ADICR014.B.CBLD = 0;

DMA_ADICR014.B.CBLS = 8;

DMA_CHCSR014.B.CICH = 1; // Clear the interrupt flag of DMA channel

// SRC_DMACH14.U = 0x00000401; // Enable the DMA interrupt on CPU0 with 63(3F) as SRPN. This is not working... if this is moved to DMA the system behaves normal but DMA non functional.

DMA_CHCFGR014.B.CHDW = 0; // DMA Channel width set data width 0-8bits, 1-16bits, 2-32bits etc..

DMA_CHCFGR014.B.CHMODE = 1; // DMA Transfer mode set 0-single mode, 1-continues mode (1- keeps DMA ECH flag enabled after complete transfer)

DMA_CHCFGR014.B.RROAT = 0; // DMA next request only after current transer

DMA_CHCFGR014.B.PRSEL = 0; // DMA in daicy chain mode 0-No, 1-Yes

DMA_CHCFGR014.B.TREL = 16; // No.of data to be sent/moved in one DMA transfer

DMA_CHCFGR014.B.DMAPRIO = 3;

// DMA_CHCSR014.B.SIT = 1; // Enable DMA module interrupt

DMA_TSR014.B.DCH = 0; // Disable DMA software transfer mode

DMA_TSR014.B.ECH = 1; // Enable DMA hardware transfer mode (required for peripherals data move)


ASCLIN3_TXDATA.U = 'H';
//Initiate 1st by to generate UART TX FIFO interrupt to DMA


// _install_int_handler((unsigned char)1, (void (*) (int)) DMA_ISR, 0);

}